What Is The Function Of The Ins Register In Bs2
BASIC Postage®
& other microcontrollers
by Parallax, Inc.
At left is the pinout of the bs2-ic 24-pin module devised by Parallax around a 28-pin surface-mountain PIC16C57C by Microchip. xvi digital I/O pins (P0 to P15) are individually accessible in the PBASIC language designed for the BS2. They can too be accessed all at in one case via a 16-bit register (INS/OUTS) or as one of two separate 8-flake buses, or as one of four iv-bit ports. Applications may likewise use a "virtual pivot" (number xvi) for asynchronous series communications through the port usually used for programming and debugging, actually using the pins 1 and 2 on the BS2 board, marked SOUT for output (cf. SEROUT) and SIN for input (cf. SERIN).
- (2014-04-17) Basic Postage "HomeWork Lath" USB (#555-28188)
A review of an inexpensive microcontroller starter set up. -
At $40, this evaluation kit (as well available at your local Radio-Shack store) is $10 less expensive than the bs2-ic Module built into it, even though it includes a $four USB A to Mini B Cable and a petty solderless breadboard, (and x 22-gauge jumper wires, for expert measure).
Other Similar Parallax Products :
The downside is that the "HomeWork Board" can't be used to program an bodily BS2 for permanent installation in a less bulky standalone projection.
To exercise that, y'all'd need a 28803 board which goes for $99 and includes a bs2-ic in a socket (to program several microcontrollers repeatedly, information technology might be wise to invest in a 24-pin ZIF socket for "zero insertion force"). Otherwise, the 28803 and the board we're reviewing here are equally suited as starter sets. There are legacy serial versions of both units, which we'll ignore hither.
Also, if y'all want to beginning straight with a better Parallax module from the table below, you'll have to purchase information technology separately, provide your ain 22-gauge jumper wires ($i) buy a USB cable ($4) and get the aforementioned carrier-board with no module on it ($70). This would add up to more than $130, plus shipping.
Featuresof 24-pivot BASIC-Postage modules (16 I/O pins + 2 serial ports) Name (2014) Microcontroller Clock Speed Run Slumber BS2 $49 PIC16C57c 20 MHz 4000 three mA 50 uA BS2e $54 SX28AC xx MHz 4000 25 mA 200 uA BS2sx $59 50 MHz 10000 lx mA 500 uA BS2pe $75 Ubicom
SX48AC8 MHz 5000 xv mA 150 uA BS2p $79 20 MHz 12000 40 mA 350 uA BS2px $79 32 MHz 19000 55 mA 450 uA Listed in the "speed" cavalcade is the typical number of PBASIC instructions executed per 2d. Like an older BS1 module (and/or the depression-price BS1 evaluation lath) a stand-alone BS2 would only demand a half dozen V to 12 V DC power supply. The other units require half-dozen V to 7.5 Five DC.
Opening the box and getting started :
The 555-28188 comes with four stick-on rubber feet to be placed adjacent to the corner holes (which are meant for stand-off screw posts, if yous decide to put the lath in a protective enclosure after).
The instructions are silk-screened on the board's flipside. They read:
Before you connect your board:
1. Install complimentary software:
http://www.parallax.com/basicstampsoftware
2. In the software, click
Assistance > Bones Postage Assist...
3. Follow the Getting Started steps.Demand Tech Support?
back up@parallax.com
forums.parallax.comFind Stamps in Course activities for the 18-carat
Bones Stamp 2 that is congenital into this lath:
world wide web.parallax.com/educationYou should just connect the lath to your computer (using the USB cablevision provided) after installing the Parallax software on the calculator and putting in a fresh 9V battery (not included).
The installation puts a "Basic Stamp Editor v2.5.3" (or perchance some other version number) on the run carte du jour but not on your desktop (copy the icon from the showtime menu to your desktop and/or taskbar if you so desire). The first time y'all run that software, it asks yous if you lot want to associate the related file types to it (.bs1 .bs2 .bse .bsx .bsp .bpe .bpx). Allowing information technology to practise so will simplify your life (those file types are not of any use outside the Basic Postage stamp world, anyway). At startup, yous're shown one of 36 "tips of the day". The first of these doesn't apply to USB boards but it mentions incidentally that in that location's an online manual. I quote:
- Use a standard straight-through serial cable to program the BASIC Stamp. A cypher-modem volition not work. If y'all're conscientious, you tin can brand your own cable... but follow the wiring diagram in the BASIC Stamp Transmission v2.0.
Following the instructions on the behind of the lath, nosotros click the Help menu and choose the beginning item in information technology ("BASIC Stamp Help..."). So, we click "Getting Started" on the left-hand column.
The first task is to identify your board. The board reviewed here corresponds to the quaternary picture listed (the last one in the v2.v.3 revision of the software). Just click the "side by side" push corresponding to that picture and perform the setup tasks described, starting with affixing the rubber feet (in example you've resisted the temptation to do and then before).
For the initial "Run/Identify examination", you should wait a few seconds later the USB cablevision is plugged-in for the first time ever (this gives your computer a fiddling bit of fourth dimension to install the proper drivers and flash the bulletin "Device is now ready to use" when that's done). Information technology's useful to know that the F6 key tin can exist used to perform the "Run/Place test" whenever the BS advice sofware is upwardly and running.
Since the unit has no power switch, you must disconnect the battery to plow information technology off. All the same, it'southward virtually impossible not to discover that one of the contacts comes off more easily than the other, so that you can just get out one side plugged-in and rotate the battery to switch the unit on and off (albeit unreliably so). I've seen at to the lowest degree i other person do that publicly, at the terminate of a video-proof that people do have fun with this thing (see Sorting M&Ms past color).
A more reliable low-price solution, without defacing the board, is to connect the battery vertically to merely ane contact (I prefer the exterior one, the negative footing) and close the circuit with a bombardment snap connector cut in half, with some switch soldered betwixt its two leads. Either that or utilise an unbutchered snap obtain a pair of wires which can connected (with am on/off switch) to any suitable DC power source (at that place's a squeamish low-drop LM2940L voltage regulator on board, and so voltage requirements for an outside power supply shouldn't be too strict).
I decided to base my own solution on a 9V power supply with an "M" plug (5.v mm OD, ii.i mm ID, positive center) specifically marketed for Arduino microcontroller boards.
Since not all such units are created equal (there are a few horror stories floating effectually) I decided to proceed charily and ordered first from Amazon a made-in-Communist china unit of measurement with great reviews, rated 9V 650 mA (for $six.50 + $ii.99 shipping). Not but does this picayune switching power supply work equally it should but information technology has a very overnice form factor which accomodates crowded power strips. The Chinese manufacturers goes by the name of Super Power Supply® and they ship online orders to the U.s.a. market from an address in Indiana (8748 E. 3rd Street, Indianapolis, IN 46226-6516). I was so pleased with their production that I tried to gild more from them. As I couldn't discover the cute fiddling affair in their catalog, I settled for the closest thing (SKU 06-861) rated 9V and 1000mA, although the moving picture showed a lousy grade factor. I ordered two units which arrived in my Los Angeles mailbox 3 days later. I was pleasantly surprised to discover that they were identical to the one I had, in every respect except a 50% higher current rating on the label! I paid $14.27 ($4.89 per unit plus $four.49 S&H).
By itself, the board draws well-nigh 9.i mA (measured) at residuum when powered with a 9 Five battery. The TL082 which we shall soon add as part of our start "existent" interface (converting digital PWM into a make clean analog signal) will depict an additional 2.5 mA at residuum...
Wiring some Standard Interfaces
Earlier I even touched this unit or looked at the online documentation, I had a few fun applications in mind for this initial review. One of them was generating DTMF tones. I was therefore shocked and amused to discover that this idea is and then mutual that one of the 42 commands in the PBASIC language (DTMFOUT) is dedicated to that and makes the software part trivial. The command generates the tone digitally in PWM mode (pulse-width modulation) since there'due south no digital-to-analog converter on lath. This can be directed to any any pin but I'll dedicate P1 to that usage (for a trivial reason which shall be given soon) and put a expert active filter on it (Parallax recommends a 2000 Hz cutoff frequency but I'll use 3300 Hz to let a larger range of audio tones, beyond TouchTone®).
It'south always a good thought to give several nonconflicting functions to the same I/O pin, specially for conclusion intended to exist permanent (we don't desire to waste pins, every bit we but have sixteen to play with). And so, I'll also attach a bicolor diode to P1 (RadioShack #276-0012) which will be xanthous (= ruby-red+green) when there's sound action, ruddy in a 0 state, greenish in a one state and unlit in the loftier-impedance land. The bicolor diode consists of a red LED and a green LED mounted in parallel with contrary polarities in a unmarried bundle with 2 pins (marked like the dark-green LED would exist if it was past itself). One manner to achieve that functionality would be to connect the bicolor LED betwixt P1 and a signal connected to both supply track by the proper current limiting resistors (equal values of 1k or so work fine because the two diodes accept similar voltage drops of 2.0 V and 2.1 V). Information technology works fine by presents one design flaw: A current of several milliamperes will drain the battery even when the unit of measurement goes into sleep mode (where merely microamperes are darwn). A ameliorate solution is to connect the bicolor LED between P1 and something whose polarity is reverse to that of P1 when P1 isn't in the high-impedance land. So, we'll brand sure that the showtime stage of our agile filter is simply an inverting amplifier in the DC authorities (at 0 Hz) so we can connect our bicolor LED (with a current-limiting resistor) between P1 and the output of that phase. At starting time, nosotros may exist satisfied with just one stage and a single capacitor.
555-28188 product page at Parallax.
Parallax Perspective: Basic Postage stamp Activity Kit (#90005) by John Williams (with manual & components). - (2014-04-22) Pulse-Width Modulation (PWM)
Converting a PWM digital signal into an analog signal. -
It's certainly not necessary to have admission to an oscilloscope to apply the Postage stamp. Nevertheless, a few oscillosope screenshots will help illustrates the concepts we have to teach now.
Pulse width modulation (PWM) denotes whatever encoding of an analog level by a digital two-level signal whose duty bicycle is proportional to the amplitude of the analog level. The method used in BasicStamps to convert an eight-bit input level is to add together the respective 8-flake value (betwixt 0 and 255) to an 8-fleck accumulator. The value of the carry bit generated past this performance is what the binary output (0 or 1) will be for the duration of the current PWM interval (a unit of time which, for the unit of measurement reviewed here, is equal to iii.eight microseconds for all PWM-related commands except one, every bit discussed below).
The dazzler of this scheme is its simplicity and the fact that it remains valid if the desired analog level changes over fourth dimension (but arrange the content of the accumulator to reflect the level change). This is how the Stamp generates siwaves and dual tones. Let's utilize an example to design, one time and for all, a proper sound output for our microcontroller.
We shall exist aiming for the same cutoff frequency as traditional telephone service, namely 3400 Hz. A elementary outset-society lowpass filter is used for the preliminary sit-in. A 3400 Hz cutoff would exist approximately achieved with a 4.7 kDue west resistor and a 10 nF capacitor. (or 47 kW and ane nF). Counting the 220W built-in resistor on the output pin and using the measured values of the components on hand for this demo, our offset exam was actually conducted with a corner frequency of 3175 Hz.
one / [ iip ( 4680 W + 220 W ) (10.23 10 -nine F) ] = 3175 Hz
The sawteeth in the bluish "sinewaves" are part of the bespeak at this signal, every bit will be discussed in nifty detail before long. Notation the differences in the amplitudes at 1000 Hz, 2000 Hz and 3000 Hz, which are a side-effect of start-order filtering and volition be all just eliminated with high-order filters.  | ' {$STAMP BS2} ' {$PBASIC 2.5} trigger Pivot 0 audio Pivot 1 OUTPUT trigger OUTPUT audio DO trigger = one trigger = 0 FREQOUT audio,1,chiliad FREQOUT audio,1,2000 FREQOUT audio,1,3000 LOOP Terminate |
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We dedicate a pin to properly trigger a Rigol DS1102E oscilloscope: The signal displayed higher up on channel one (yellowish) is meant for the scope's "external trigger" input (using a pair of clips fastened to a BNC cablevision).
Annotation that the width of the pulse tin can be precisely measured to be 184.8 the states using a higher timebase resolution (that'due south a more precise value than the "180.0 u.s.a." in the in a higher place screenshot at depression resolution). That's an interesting measurement of the time it takes to execute a very uncomplicated PBASIC step, which translates into 5400 steps per 2nd (the BS2 is advertised to execute 4000 "typical" PBASIC instructions per second).
The ascension and falling edges of the trigger signal demand not be adjacent. Identify them separately anywhere you like in your plan to examine ii different parts of the main loop in more complicated cases, without the demand to tax the scope's delayed timebase. The two triggering options tin then exist selected on the scope without reprogramming the microcontroller nether test (although information technology takes simply a few seconds to do and then).
 | We now show details of the 2000 Hz "sinewave" outburst from the to a higher place exam, along with the driving PWM digital signal (yellow trace). Transitions tin can only appear at regular intervals of iii.8 u.s. This PWM cycle, used in the algorithm described to a higher place, corresponds to 76 cycles of the BS2 clock, at the advertised rate of 20 MHz. |
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In this screenshot, the telescopic shows the right duration (4 units = 15.2 us) of the first whole interval on the screen and underestimates the second ane by 5% (it can observe the right value of 3.800 usa using shorter time-scales).
This 3.8 us abiding interval, corresponding to a PWM sampling frequency of about 263.16 kHz, is the same for all PWM waves produced past the BS2 firmware (single frequency, double frequencies or touchtone). Unexplicably, it's slightly longer (4.four us) for the PWM command itself, which merely produces the PWM equivalent of a static level.
To brand it like shooting fish in a barrel on yourself, 1 cost-effective style to get beyond the above first-order filter is to utilize a commercial DSL filter, which is normally designed to accept the aforementioned corner frequency (around 3400 Hz). Such filters are typically third-order or better...
Using PWM for Analog Output (BASIC Stamp I Application Notes).
- (2014-05-18) Variable-Gain Amplifier (VGA) for a PWM Bespeak
The trick is to attenuate the PWM square wave before filtering it. -
Then far, nosotros have decoded the PWM digital output from the microccontroller into a skillful analog signal. The BasicStamp firmware could easily have encoded different analog levels in its PWM tones. Unfortunately, it did not. So, we accept to find some hardware solution to the problem of allowing software to control the sound volume.
The analog counterpart of what we are after is chosen a voltage-controlled variable-proceeds amplifier. As a purely analog projection, that would be a adequately intricate endeavor, well beyond our electric current scope. However, nosotros tin simplify things profoundly by noticing that a PWM signal tin can but be used to chop up (turn on and off) some constant DC level different from the whole supply voltage. Filtering that square moving ridge will result in a betoken proportional to the DC level used.
The showtime step is to produce a steady analog voltage from a PWM signal on some other pivot. To do that we use the 2nd loftier-impedance opamp in the IC (TL082 or TL072) whose first half we've already used as an active filter. Allow's dedicate 1 pivot (which nosotros'll phone call LEVEL) to the audio gain command. Nosotros connect LEVEL to the not-inverting input of the operational amplifier wired as a voltage follower (i.e., the output is connected to the inverting input). Let'due south now connect a 22 nF capacitor, say, to that pin (and nothing else, non even a probe tip).
The charge on the capacitor has substantially nowhere to get when the microcontroller pin is in its loftier-impedance state. And then, we take a constant voltage at the output of the operational amplifier which will take a very long time to decay... Much more than than what we need to maintain the output volume of every divide tone, for a few seconds, at most.
With a metal-pic capacitor of 22.viii nF on the breadboard, I measured a fourth dimension constant of 3528 s (nearly 1 hour) which translates into a combined resistance of 155 KWestward for all pathes to ground in this casual test. That would mean that the book of a continuous tone would subtract at a negligible rate of 0.0024 dB/due south (three dB after 20 minutes).
Note that we should non utilize the OUTPUT command for the LEVEL pin. Doing so would forcefulness the state of the pin low or high for a substantial amount of time (at least 184.iv us, remember?) and we don't demand that; the PWM command makes the pin an output pin only for the elapsing of its execution, which is exactly what we want.
- (2014-06-22) Using an alphanumeric LCD with a BASIC Postage stamp ii
With a BS2 (or equivalent) PBASIC offers no congenital-in LCD support. -
Equally this is really a continuation of the previous educational introduction, using the inexpensive HomeWork Board equivalent to a Basic Postage stamp II (BS2) we'll practise more than piece of work to really get to the bottom of things.
Our advantage for not cutting corners will be a couple of final answers to software and hardware issues which are very oft desperately butchered...
For units beyond the BS2, Parallax provides iii specific PBASIC commands which facilitate 4-bit parallel interfacing with an LCD (liquid crystal display) driven past the manufacture-standard Hitachi HD44780 grapheme-LCD controller (namely, LCDCMD, LCDIN and LCDOUT). Nosotros'll find that the scheme has one imperfection, in theory if not in exercise (a 4th specialized command should accept been provided for the early steps of initialization, accomplished in viii-bit way with an irrelevant depression-crumb).
The HD44780-compatible LCDs are unremarkably available in several formats:
- 1 line of 16 characters. [ $3.76 ]
- 2 lines of 16 characters. [ $one.85 | [ $iii.71 ]
- iv lines of 20 characters. [ $v.35 | $six.46 | $6.46 ]
We'll make our wiring compatible with one of the configurations supported by Parallax in the aforementioned specialized LCD primitives. Then, nosotros'll discuss PBASIC software to support that configuration and turn the whole thing into the educational experience information technology was meant to be.
7 pins are commonly used to interface with the LCD. Some people utilize simply half dozen pins for one-mode communications with an LCD (write-only) by tying to basis the R/W pin (number v on the standard LCD connector). I don't recommend that shortcut at all. With the sole exception of the enable pivot (number vi on the LCD connector) all pins are used only temporarily by the LCD and tin be shared by other devices.
When the LCD display is not accessed, P12-P15 tin be used as a 4-flake passenger vehicle for other purposes, keeping in mind that this bus is not put into a high-impedance state when the LCD is disabled merely features 30k pull-upwards resistors instead (equally discussed below). 
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LCD units without backlighting have connectors with only 14 pins instead of . Pin 15 is the anode (+) of the backlight and pin 16 is the cathode (-). Connect 16 to footing (Vss) and connect 16 to the positive 5V ability rail through a current-limiting resistor.
In the BS2, every I/O pins is protected by a resistor of 270 ohms or so, which is great for a xanthous-dark-green LED backlight. In my test unit of measurement, the back (which such a protected pin will bulldoze direct at vi.74 mA with a voltage drop of 3.15 V).
The potentiometer on pin iii of the connector (often dubbed "contrast") is crucial. Information technology establishes the Vee voltage of the LCD, which should be ajusted according to room temperature for all-time results. If Vee is too low, off-pixels are visible. By increasing Vee, an optimal voltage is reached where the off-pixels disappear, but barely so (increasing the voltage across this would brand the on-pixels fade away). At this writing for example, room temperature is 28°C (83°F is typical of Los Angeles in June) and the optimal Vee for my test unit of measurement is 780 mV (better described as -4.2 V with respect to the LCD anode). Because the optimal "Vee" depends on temperature, it's somewhat unpredictable and the user should exist able to conform it with a trimmer. If the unit is meant to operate in various environments, an automatic compensation for temperature and/or supply voltage could be considered (especially when using a microcontroller with a spare analog voltage control). Sometimes, the all-time voltage can be negative with respect to the cathode also (especially for 3.three 5 circuits) and a negative rail becomes indispensable for best results.
Different LCD Formats :
On a multi-line LCD character display, the positions of the characters in a given line are always numbered consecutively from left to right. What varies from i LCD to the next are the numbers assigned to the first character of each line.
The displays that feature iv lines of 20 characters behave every bit if they consisted of 2 lines of 40 characters. whose second halves appear as the third and fourth lines of the actual screen, which is filled by autoincrementing from 0 to 79 (and back to 0) as follows:
| 0 | 1 | two | 3 | iv | 5 | half-dozen | 7 | 8 | ix | x | 11 | 12 | 13 | 14 | 15 | sixteen | 17 | xviii | 19 |
| twoscore | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | fifty | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 |
| 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 |
| sixty | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 |
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Even so, this is non the way direct-access indices are organized. Instead, the beginnings of the 2 lines are respectively at addresses 0 and 64. The 2 sets of forbidden entry points at the "end" of either line (40-63 and 104-127) behave exactly like the valid beginning of the next line (64 and 0, respectively). Both forbidden sets are skipped when the LCD is accessed sequentially, by autoincrementing.
| 0 | ane | 2 | three | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | fifteen | 16 | 17 | 18 | xix |
| 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 |
| 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | thirty | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 |
| 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 |
 | At left is the standard 5x8 matrix font for the HD44780. It's sometimes called a 5x7 font because the lesser row is bare in all standard characters to leave room for an underscore cursor. Yet, this demand non be the case for custom characters, specially in applications where the underscore cursor isn't used. The HD44780 provides only 64 bytes of CGRAM (character generator RAM) for custom characters. In this 5x8 format, that'southward enough for 8 custom characters (each 5-chip row uses a byte) encoded from 0 to seven at the highlighted positions in the table. In the rare 5x11 format (not covered here) those 64 bytes would only permit 5 custom characters, numbered from 0 to 4, with nine leftover bytes. |
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Like DDRAM (information display RAM) the 64 locations of CGRAM are accessible by accost and successive writes will cause an autoincrement to allow access to the next location. As well like DDRAM, this autoincrement wraps around to the beginning of the available infinite. If you lot must know, and then practise the codes of the custom characters. (In practice, this means that the characters you defined for codes 0,1,2... will also be available at 8,9,10...)
| Name | RS | RW | Data Passenger vehicle | Instruction (action to perform) | msouthward |
|---|---|---|---|---|---|
| clear | 0 | 0 | 0000 0001 | Clear every display byte, reset cursor. | 1640 |
| home | 0 | 0 | 0000 001. | Reset display shift, reset cursor. | 1640 |
| entry | 0 | 0 | 0000 01as | Autoincrement (a=1). Allow shift (s=1). | 40 |
| show | 0 | 0 | 0000 1dub | Display (d), underscore (u), blinker (b). | 40 |
| motility | 0 | 0 | 0001 cm.. | Cursor (c=0) or display. Left (g=0) or right. | 40 |
| set up | 0 | 0 | 001w nf.. | 4-chip (westward=0). Single line (n=0). 5x8 dots (f=0). | 40 |
| cgram | 0 | 0 | 01,accost | half-dozen-bit address in character-generator space. | forty |
| ddram | 0 | 0 | 1, accost | Set seven-bit address in data-display space. | 40 |
| busy | 0 | one | BF,accost | Fetch current address ("busy flag" in MSBit). | 0 |
| write | i | 0 | data | Write eight-chip data to current accost. | twoscore |
| read | one | ane | data | Read 8-fleck data from current address. | 40 |
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- a (autoincrement flag) pertains to DDRAM admission only. a=one is the normal style whereby successive accesses correspond to indices in increasing club. To go backwards, use autodecrement mode (a=0).
The HD44780 data bus has pull-up resistors :
Let'south nvestigate the loftier-speed protocol which avoids undue delays for a fast microntroller (this doesn't utilise to the BS2 running PBASIC, with a single exception which is easily disposed of). In the process of this investigation, I discovered that the LCD'due south enable pin (pin half dozen on the LCD connector, often called "E" and dubbed LCD in the source code provided here) doesn't put the LCD data passenger vehicle in a high-impedance state, as expected. Instead, the data lines sport 30k pull-upwardly resistors, which the designer should proceed in listen when sharing this motorcoach with other devices.
In one case the LCD has been properly initialized, we may endeavour to fourth dimension the longest LCD instruction to run across if any extra delays are needed on the BS2. The following BS2 plan fragment is meant to visualize on the oscilloscope what time is leftover in the worst example...
Do ' Testing BF = Db7 with an oscilloscope : char = LCDclr ' %00000001 (Clear LCD) is the SLOWEST control GOSUB LCDctrl ' Transport command (and leave RS low) DIRD = %0000 ' Employ 4-bit autobus D as input (pins 12,13,14,15) Loftier rw ' This ascension edge of RW will trigger the scope Loftier lcd ' Enable LCD PAUSE one ' Monitor Db7 = BF with a 10k pull-down resistor Low lcd ' Test complete, disable LCD LOW rw ' Back to write mode LOOP ' Repeat (more than than 200 times per 2nd) -
The highlighted part of that program corresponds to the oscilogram below (the xanthous trace is R/W). The ten chiliadWestward external pull-down resistor on BF reveals the presence of the aforementioned 30k internal pull-up resistor.
| The oscillogram below shows how an LCD unit driven by an HD44780 makes a weak attempt to control the data bus through internal 30k resistors (fighting an external 10k pull-downward resistor installed for the purpose) even when the LCD unit is disables!  | The 30k value itself tin can be deduced from the screenshot at left, where a 25% level is observed on Db7 = BF (blue trace) as the pull-up resistor fights the external 10k pull-downwardly resistor (temporarily installed for this exam only). Too, the failure of the BF signal from the LCD to accomplish the 100% logic level (which doesn't exist without the pull-downwardly resistor) tin exist attributed to an output impedance of 1.5k or so. |
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Some sloppy designers advocate grounding R/W nether the dubious pretense of "saving" a pin and/or a cablevision wire (the latter at the cost of performing the grounding directly on the LCD connector).
If reading the LCD is permanently disabled by grounding R/Due west, the LCD can't be used at full speed in automobile linguistic communication. PBASIC, on the other manus, is so wearisome that the issue merely arises in the "clear-screen" command (used in the above oscilloscope test). The "write-only" utilize in PBASIC of an HD44780-driven LCD is thus totally safe if one simply waits an additional ii milliseconds after immigration the screen. That's all there is to information technology...
With a microcontroller programmed in assembly language however, it'south more satisfying to drive the LCD in the proper high-speed fashion (reading BF before writing to the LCD).
When the microcontroller is in sleep mode, output pins are still driven merely will go out for nigh xviii ms every ii.304 s. During those regular outages, spurious strobes could occur on the LCD's "enable" pin if nosotros didn't install a pull-downwardly resistor on that pivot (which is the only one permanently defended to the LCD unit, too the backlight pin).
"Jitter" reveals the exact frequency of the LCD local clock:
Jitter is the miracle whereby events which could naively be expected to happen repeatedly at a anticipated time are actually observed to exist randomly early or late, within a definte interval of measurable width. (In some contexts, that's also called phase noise.)
In the above, ane can detect an obvious jitter on the falling edge of the BF signal (blue trace). Its width can easily be measured to exist most 17.6 usa (with the oscilloscope at 2us per division observe the jitter for several seconds, placing one cursor on its lower limit and another on the upper 1). If we assume that the jitter is due to the lack of synchronization of the BS2 clock and the microcontroller clock, and then the width of the jitter is equal to a whole number of cycles of the LCD clock (presumably, the time it takes the HD44780 to execute each cycle of a waiting loop). This means the clock of the tested LCD unit of measurement is a multiple of 56.8 kHz or so. As the datasheet of the HD44780 specify a clock frequency between 190 kHz and 250 kHz, we may expect the clock frequency of that particular unit to be well-nigh 227 kHz and deduce that the HD44780 can't pinpoint the time of external events to an accuracy amend than 4 clock cycles, which seems reasonable...
How to command a HD44780-based Character-LCD by Peter Ouwehand (1995-2012).
HD44780 LCD Starter Guide by Embedded Systems Blueprint Laboratory (Stanford, EE281, Fall 2001).
LCD Initilization past Donald Weiman (2009-2012).
HD44780 LCD Displays by Myke Predko (1998).
Controlling a LCD display with the Bones-Postage stamp ii (scout for inaccuracies).
ProtoStack Tutorial: HD44780 LCD Displays by Daniel and Sandy Garcia (Brisbane, Australia, 2010).
LCD Interfacing Tutorial: CGRAM (creating custom characters) by Rickey.
Nokia 5110: 48 by 84 matrix LCD, PCD8544 driver by Phillips. - (2014-04-xix) Keypad with a Basic Stamp
Giving nascence to a standalone HW1 past cutting its USB umbilical string. -
Our goal now is to plough the HomeWork Board (HWB) into a controlling device which can be operated without its USB umbilical cord. We're already halfway into this with the LCD provided above. In this section, we'll complete the process by endowing the unit with a 16-fundamental keypad. After this, the resulting standalone device deserves an enclosure and a proper name: HW1.
I'll install an off-the-shelf 16-cardinal keyboard (the usual telephone keys plus an ABCD column corresponding to the four extra standard touchtones). The supporting software volition recognize 136 possible input combinations from this: 16 single keys and 120 combinations of ii keys pressed simultaneously. The idea volition then be to use this in a carefully designed bill of fare system, with or without the feedback of the LCD display.
Parallax datasheet: 4x4 Matrix Membrane Keypad #27899
- (2014-05-23) Cheap Sonar Sensor
Billowy ultrasound (twoscore kHz) off an object to measure its distance.
 | The HC-SR04 is a 4-pin device. Too the ability rails (labeled Vcc and GND) at that place's an input pin labeled TRIG and an outpout pivot labeled Repeat. The device consists of a microcontroller driving two identical audio-visual transducers working at a nominal frequency of 40 kHz (ultrasound). It sends an eight-wheel sound burst and measures the time it takes to receive the echo. |
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The unit is activated by a positive pulse on the TRIG pin and responds with a positive pulse on the ECHO pin later a fixed amount of time (on my unit, the leading edge of Echo comes 466 us afterward the falling edge of TRIG). The width of that pulse is the fourth dimension it took to receive an echo (i.e., twice the distance between the sensor and the object, divided by the speed of sound).
The duration of the trigger pulse is irrelevant as long as information technology exceeds the minimum specified by the manufacturer, namely, 10 us (although the exam unit of measurement seems to trigger reliably on pulses every bit short equally v or 6 us).
This demo lights up an LED when the measured altitude is 204 mm or less:
' {$STAMP BS2} ' {$PBASIC 2.5} trig PIN 1 echo PIN 2 led PIN 3 time VAR Discussion Low trig ' Equivalent to OUTPUT trig : trig=0 INPUT echo LOW led Practice PULSOUT trig,25 ' 50 us on a BS2 (10 u.s.a. on a BS2sx) PULSIN echo,1,time ' Receive pulse width IF time <= 300 THEN ' 204 mm at 340 m/s led=ane : ELSE : led=0 : ENDIF LOOPConspicuously, the unit could take been designed to combine the output and input functions on a single pin. Such single-pivot devices are indeed bachelor simply they happen to be much more expensive than the unit reviewed hither...
SainSmart HC-SR04 on Amazon ($v.81). by Sparkfun.
PING))) Ultrasonic Distance Sensor by Parallax (Unmarried-pivot device, $29.99).
Ultrasound sensors on SensorWiki: Time, speed (Doppler shift) and attenuation of ultrasound. -
(2014-04-22) Synchronous Serial Communications
Instance: Real-time clock (RTC) using the I2C jitney. -
Our introduction to the I2C protocol will be based on a unit of measurement which contains two contained I2C nodes; a real-fourth dimension clock and a mid-sized EEPROM (4096 bytes of non-volatile memory).
 | The tiny board at left retails below $vi (with shipping). It'south congenital around a DS3231 with an integrated temperature-compensated crystal oscillator (TCXO). On the "32K" pin is the output of the 32768 Hz oscillator (300 ns rising fourth dimension, 32% duty, xv ns fall). The programmable SQW output pin tin evangelize a 1 Hz signal (300 ns rise, xx ns fall, l%). |
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Straight out of the box, without using its digital trimming capabilities, the DS3231 has a 2 ppm accurateness (betwixt 0°C and forty°C) which translates into 1.2 s per week, or ane minute per year. To measure out the accurateness of the clock in just a few minutes, y'all may use the stable ane Hz signal (often termed PPS for "pulse per 2nd") from a GPS receiver. Use that signal to trigger a digital oscilloscope and observe the 32768 Hz output with the timebase set at ii usa per division (so you tin ever run into several wavefronts on the screen). The signal will slowly pitter-patter to the left (if the clock is fast) or to the right (if it'southward tedious). Measure out the time T be the time it takes for the trace to migrate on the screen by a distance corresponding to a given interval (1 microsecond, say). The relative accuracy of the clock is simply t/T. For example, with the factory settings ("crumbling register" set to zero) I plant that the trace was drifting to the left on the screen by 2.5 us in 36.32 seconds at a temperature of 31¼°C (according to the bit, just probably more similar 29°8) and so that clock is too fast by the following relative amount:
(2.5 us) / (36 s) = 0.07 ppm = 2 seconds per year
A few minutes afterwards, at the same temperature, it took only 26 seconds for the same migrate (that's ane ppm). Then the drift seemed to end when the temperature (every bit measured by the bit itself) dropped only a quarter of a degree... The data canvas says that the oscillator can exist trimmed in steps of roughly 0.ane ppm (the user-supplied correction is stored in annals $ten termed "aging register" and is updated every 64 seconds or upon request). If establish the influence of the aging register, if whatsoever, to be far less than that in the conditions described in a higher place. Information technology looks as though the chip is significantly more than precise than what'south described in the datasheet, but less adjustable... My outset impression virtually the unit exam is that its untrimmed performance is at the best level that digital trimming would let, co-ordinate to the datasheet. The influence of digital trimming, if any, is certainly far below the 0.1 ppm per step quoted in the datasheet. My observations are thus consequent with the fact that the unit of measurement I am looking at was trimmed at the factory to the best precision the hardware would allow (roughly 0.1 ppm) with user-adjustable trimming now turned off.
The venerable DS1307 doesn't brainstorm to approach that level of performance of the DS3231. (In typical applications, the DS1307 relies on an uncompensated external 32768 Hz crystal.)
Too the real-time clock itself, the higher up DS3231 board (like its DS1307-based predecessors) includes an independent 32 kbit EEPROM (4096 bytes of non-volatile data) which could be another good didactic I2C case, admitting a duller 1... Earlier I got may hands on the part, my intention was to use that EEPROM to shop aging information on it (the variation of optimal digital trimming over the years). Considering of the to a higher place considerations, this is at present moot.
1 nice feature of the DS1307 is that is has static RAM (SRAM) maintained past the clock bombardment on the portion of the 8-chip accost space not used by the actual RTC registers. The DS3231 doesn't take that, only there is an otherwise identical IC (the DS3232) which does.
Different the DS1307, the DS3231/DS3232 features a century toggle (located at the about pregnant position of the month-number byte). This is toggled whenever the century changes, to deal with potential bugs at the beginnings of the years 2100, 2200, etc. (Remember the Y2K millennium bug?)
To be able to properly decide leap years, a chip like that would need to keep rails of the century modulo 4. That's but 2 bits, but the DS3231 doesn't have them. Instead, the DS3231 uses the Julian rule (which call for every yr divisible by iv to be a bound year) and ignores the Gregorian modification to that rule used in our mod calendar (where years divisible by 100 aren't jump years unless they are also divisible by 400). The DS3231 will therefore fail on the first day of March in 2100, 2200, 2300, 2500...
The outset bad day for the DS3231 comes only 59 days after the DS1307 will fail for lack of a "century toggle".
However, a microcontroller using the DS3231 tin still read the right date from it essentially forever if it'southward simply allowed to read the clock at to the lowest degree one time per century! I am ignoring practical details such as battery life and EEPROM information retention period in this intellectual exercise...
To do then, we but compare the twenty-four hour period of the calendar week maintained by the DS3231 (flawlessly) to what tin be computed from the date (including the upper digits of the year, which the microntroller can proceed update for itself by reading the century toggle chip, if immune to practise so at least in one case per century).
Any discrepancy is settled by adding to the date a number of days (from 0 to half-dozen) equal to the difference between the computed weekday and the weekday stored on the flake (the latter should never be adjusted). This effectively cancels erroneous leap days (Feb. 29) which the DS3231 would wrongly insert on 3 of every 4 century years (2100, 2200, 2300, 2500, etc.). This algorithm allows the right date to be determined without ambiguity modulo a period of 400 consecutive years (one Gregorian flow).
If the above algorithm is always executed before the fourth dimension/date is displayed, there isn't even a demand to update the information stored on the scrap (but it's prudent to and then, of course). If you don't look to be around in March 2100, you may safely ignore all of the above but you shouldn't...
The I2C (Inter IC) Double-decker
The oscillogram below shows the transfer of a $56 byte (standing for the value 56 in BCD) from a "slave" IC (a DS3231 real-time clock) to a Basic Stamp 2 "primary" (BS2) over an I2C bus. 9 clock pulses are sent on the SCL line (yellow) past the BS2 executing a fast-paced control: SHIFTIN sda, scl, MSBPRE, [frame\ix]Normally, the BS2 should be listening for the showtime 8 bits and pulling SDA depression to ask for more data. However, this is the last byte of a transfer and the master must send a "1" bit (a NACK signal) which is exactly like pretending to listen for a ninth bit! | This is office of a clock program where nosotros only demand to fetch a unmarried flake (the parity of the least meaning digit in the count of seconds) to check as fast equally possible whether an update is needed, so any pull a fast one on goes... Otherwise, we'd have to perform an 8-fleck transaction in one direction and a ane-bit acknowledgement in the other. The slave changes the state of the data line (SDA) in blue, just afterward each clock pulse. Not visible at this time-scale is a reaction lag of virtually 350 ns from the RTC chip and a rise time (10-90%) of 165 ns with a 2.15 m W pull-upward resistor on SDA (designed for 400 kHz "Fm mode" employ). |
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As examplified to a higher place, the BS2 can be used to communicate over an I2C motorbus as a master (not as a slave, which is a much more demanding task). The basic stride of the above example cannot be adjusted on the BS2 platform (accept information technology or get out information technology). The basic BS2 clock rate for IC2 communications is xvi.six kHz The width of each clock pulse is xiv.24 us and the interval between them is 46 us. Most all I2C devices are rated for at least 100 kHz and will very hands accomodate the higher up step.
Note that the BS2 uses button-pull on both bus lines in the relevant archaic, instead of the open up-collector architecture I2C is based on. Models beyond the BS2 characteristic PBASIC primitives specifically designed for I2C (namely I2CIN and I2COUT) only we are not reviewing those hither.
This isn't much of a problem in exercise, as long as the BS2 chief never pushes a hard "1" on a bus line (by contrast with a soft "1" produced past the high-impedance "input" state) at times when the I2C protocol allows a slave to pull is depression.
That circumstance can hardly happen at all on the SCL line, which virtually slave don't even have the circuitry to treat information technology as anything only an input. A few slaves may be able to "hold the clock" low to tell a fast chief to wait during high-speed transfers. This blazon of protocal is beyond the telescopic of this article.
When the main (the BS2) is speaking on the SDA line, all slaves are listening and it makes very little difference whether the BS2 is using open-collector or push-pull logic (the only difference on an oscilloscop is that rising times are faster, with a possible overshoot, when push-pull is used).
Don't even think of allowing the BS2 to share an I2C bus with other masters or with slaves that tin can "concur the clock".
On our side of things, information technology's essential never to let the BS2 attempt to write anything just a zero at a fourth dimension when it's supposed to exist listening on the SDA line (simply doesn't care virtually the information). Or else a status may issue which is technically a bad brusk circuit (no physical damage will result simply because of the BS2'due south built-in protection resistors on I/O pins). In practice, this give-and-take of caution only applies to the writing analogue of the 9-flake read discussed above. The 9th bit in an I2C write is supposed to exist written by the slave (and it's usually low). If the BS2 chooses to overwrite that bit, it better be a zero. In other words, don't Ever use the post-obit instruction unless you are admittedly sure that "frame" is fifty-fifty!
SHIFTOUT sda, scl, MSBFIRST, [frame\ix]
| Below is a close-up view of the acknowledgment by a DS3231 chip of an I2C request past a Basic Postage 2. | Because its pin is protected by a substantial resistance, the BS2 can pull the SDA double-decker line but so low (696 mV) against a two.xv thousand pull-up resistor. Afterwards the falling edge of the positive pulse on SDA, an intermediary level (476 mV here, but it's sensitive to fidgeting with the breadboard) is rapidly reached which is maintained for a surprisingly long fourth dimension (165 usa) |
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The I2C standard tin reach synchronous serial communications betwixt many ICs over a distance of a few meters, using only a single pair of shared lines (likewise the two power rail).
Every transfer over an I2C bus begins with a Get-go betoken (more than about that later) followed by a control byte containing a 7-bit lawmaking followed by a ane-bit mode (0=write, 1=read). The 7-bit code can exist one of 112 short slave addresses or it tin can exist one of the 16 commands tabulated next, which ordinary (7-bit) I2C slave devices may safely ignore.
Four of these codes ($04-$07) are actually part of a rarely-used 10-bit addressing scheme, which adds 1024 addresses (for a grand total of 1136 possible slave addresses). This was introduced in 1992, as part of the start standardization of I2C (launched past Philips 10 years earlier) in anticipation of a yet-to-come crowding of the I2C infinite.
I'thou not enlightened of a single commercial I2C chip with a 10-bit address simply I'1000 withal providing total software support for it here (without slowing downwardly 7-bit operations past any significant corporeality).
Several 10-bit slaves may reply to a $04-$07 command lawmaking, but at most one should acknowledge the accompanying extension byte.
Leading zeroes (in binary or hexadecimal) can be essential to avert confusion between long (x-chip) and short (7-bit) addresses. $48 and $048 (%1001000 and %0001001000) are different. Some misguided authors are ignoring the very existent possibility of long (x-bit) I2C addresses less than or equal to %0001111111. There are no "reserved" x-bit addresses; the 1024 possibilities are available.
Note that the designers of the I2C protocol saw information technology fit to specify that the second part of a 10-bit address should only exist given once at the beginning of a combined transaction (read-write=read). This improves the throughput of the bus a picayune just forces 10-bit slaves to follow-upwards on transactions that partially match their accost in club not to error for their full address the combination of their own prefix with some random information (which typically would happen 0.4% of the time).
seven-chip Code R/W Meaning 000 0000 0 General call 000 0000 ane START byte 000 0001 - CBUS format 000 0010 - Other format (reserved) 000 0011 - Reserved for future use 000 0011 - Reserved for future use 000 0100 0 Hs mode master lawmaking test (0) 000 01xy z Hs fashion chief lawmaking xyz (one to 7) 000 0011 - Reserved for future use 111 10xy R/West 10-scrap address (xy $.25 & side by side byte) 111 1100 - Device ID 111 1101 - Reserved 111 1110 - Reserved 111 1111 - Reserved Two I2C devices with the aforementioned accost shouldn't coexist on the aforementioned omnibus.
The maximum capacitance allowed on each bus line (400 pF) restricts the physical characteristics of the coach and the number of connected devices.
The original I2C bus was introduced by Philips in 1982 for a maximal clock rate of 100 kHz (with a rarely-used slow mode express to 10 kHz). Unlike the before DS1307, the DS3231 fleck reviewed here tin can too operate in the so-called fast fashion (Fm) introduced in 1992, which allows clock speeds upwards to 400 kHz. Come across below for recent upgrades.
The 2 I2C bus lines are called clock and information and denoted past two standard 3-letter abbreviations:
- SCL : Series clock line.
- SDA : Series data line.
Both lines are open collector with pull-up resistors connected to the positive power rail (that name assumes the lines are driven past NPN transistors with grounded emitters, but other equivalent technologies tin exist used and the designation open up bleed is also mutual). The logical state of either line is thus high past default and becomes "0" only when it's actively pulled to basis past a conducting transistor.
This holds for the normal I2C bus (with a maximum clock rate of 100 kHz) and all upgrades thereof, except the ultra-fast mode introduced in 2012 (supporting clock rates up to 5 MHz) which uses button-pull logic on ii bus lines with different names (USCL and USDA).
I2C buses are rated co-ordinate to the highest clock rate they can handle Way Clock (max) Twelvemonth Structure Slow 10 kHz 1982 Open up collector Normal 100 kHz 1982 Open collector Fm Fast 400 kHz 1992 Open collector Fm+ Fast+ ane MHz 2007 Open collector Hs High-speed 3.iv MHz 1998 Open collector UFm Ultra fast 5 MHz 2012 Push-pull Atmel call their version of I2C "2-Wire Interface" (TWI). They currently do not support x-fleck addressing or loftier speeds.
The I2C bus is very like to the SMBus introduced by Intel in 1995 (the other accepted abridgement for "Arrangement Management Omnibus" is SMB; please avert "SMB bus" for grammatical reasons).
One significant difference is that SMBus allows dynamic allocation of slave addresses (for "plug and play" operation of removable devices) which is rare in the I2C world. SMB devices aren't allowed to operate at very low frequencies (which makes them unsuitable for educational I2C demonstrations where where the bus is operated manually): They accept a minimum operating frequency of ten kHz and a timeout of 35 ms. SMB devices must be operated below 100 kHz. Many implementations no non follow the official SMB recommendation of pull-up resistors of 14k or more (in 5V systems) which forces sluggish operations. In that location are too differences between immune voltages and current levels only, for the most part, both standards are compatible below 100 kHz.
Bus Masters :
Every transaction over the I2C autobus is between two nodes dubbed master and slave. Those rôles pertain to a single transaction; several nodes may exist capable of acting equally masters of the bus. When several masters tin can compete for command of the bus, every ane of them must exist a qualified multimaster willing and able to follow strict arbitration procedures. Usually, a BS2 only human action equally a singlemaster on an I2C coach where all other nodes are slaves. It takes heroic efforts to turn it into a proper multimaster.
A master obtains command of the bus by creating a first condition (namely, causing a high-to-depression transition on SDA when SCL is loftier). Information technology'southward solely responsible for generating the clock signal (SCL) and formulating requests (issuing additional START signals as needed) until information technology gives up control of the bus by creating a terminate status. A master can drive the I2C bus with arbitrarily depression speed, then a sluggish microcontroller, like the BS2, can hands exist a principal of an I2C autobus.
A well-behaved multimaster would at least need to monitor the I2C jitney continuously to know when information technology's busy (between a Start and a STOP). This function is hands handled in hardware (it would exist foolish to endeavour it in software, even using interrupts) by creating a BUSY indicator available to all potential masters sharing the autobus. The START procedure in a multimaster environment is:
- Brand sure the jitney isn't BUSY (poll hardware indicator).
- Pull SDA depression to create a Start signal.
... / ...
Slaves :
An I2C slave device must be able of recognize its own address quickly to respond to a master'southward request. A microcontroller can hardly part as a slave unless it can handle hardware interrupts, which the BS2 can't practise.
In normal synchronous information transfer, the logical country of the data bus line tin only change when the clock line is depression (a high clock thus indicates stable valid data which can be safely read by the receiver). A data transition when the clock is high indicates either a start bit (when the data line goes from high to depression) or a terminate flake (for a low to high data transition).
After the start scrap, the primary sends an 8-flake piece of data (ever starting with the most meaning bit) containing the 7-bit address of the slave it wishes to communicate with, followed by a R/Westward fleck set up to "0" if it wants to write to the slave or "i" if information technology wants to read from it. The slave so addressed should transport an acknowledge bit (ACK) by pulling SDA depression during the unabridged loftier time of the 9th clock pulse on SCL.
Once communication is established in this way, a normal transfer of information takes place in the direction previously indicated by the master, which keeps clocking the bus (not faster than the rate used for the above initial handshake). The slave is responsible for issuing an ACK fleck after each byte transferred. Failure to do so is a NACK condition, which tells the master information technology should terminate that multi-byte transaction (with a stop flake) and liberate the bus for the side by side transaction.
A slave can deny access to a main at whatsoever part of a write transaction (from the master's perspective) or at the get-go of a read asking simply past doing cypher, instead of pulling SDA low before the chief problems its ninth clock pulse. As well, a main can end a reading sequence by not pulling SDA depression earlier issuing the ninth pulse.
However, no part of the I2C protocol allows a slave to asking termination of a read sequence in one case it has started. It can either do nothing (which volition look to the primary as if the slave is sending an endless sequence of $FF) or "wrap effectually" its own address space every bit if its starting time register followed its last. For some obscure reason, the latter solution is more popular than the former.
Properly resetting a singlemaster I2C bus and its connected interfaces :
The process described below should be made part of the initialization routine of any microcontroller with a reset push or any microcontroller which can be powered down independently of some devices connected to its I2C bus.
The problem is that the microcontroller in charge could have been reset at whatever point in the middle of an I2C transaction, so a slave could be pulling SDA depression forever, waiting for a clock pulse which never comes.
Making the following procedure part of the microcontroller initialization will remedy that situation and put any interrupted interface back to its normal land after every microcontroller reset. This indispensable slice of I2C sociology is now mentioned, more than or less precisely, in the datasheets from several I2C manufacturers (including Proverb and Atmel).
The trick is to toggle SCL (up to 9 times) until SDA is brought to a high-level while SCL is high. At this signal, nosotros can simply pull SDA low to generate a start condition. I like to complete the initialization by letting SDA go high again, which creates a stop status and releases the I2C bus for normal use (in pristine condition, with both lines pulled up).
In a multimaster I2C surround and/or in an high-speed protocol where some nodes may "stretch the clock" (pulling SCL low, which prevents it from being toggled) I'm unaware of a foolproof initialization procedure like the above. The only style out would be to power-cycle the whole system in order to allow every node to reset itself (as function of its own power-up sequence).
I2C double-decker specification & user manual (Rev. 6, 4 April 2014) past NXP ("Philips Semiconductors" until 2006).
10-bit addressing
AN10441: "Level shifting techniques in I2C-passenger vehicle pattern" by NXP (2007-06-xviii).
AN97055: "Bi-directional level shifter for I2C-bus and other systems" by Herman Schutte, Philips Semiconductors (1997-08-04).
Planet Analog : The I2C Bus, by Thomas Kugelstadt (2009-06-08).
Design calculations for robust I2C communications by Rich Pell (2012-04-eighteen).
Wikipedia : I2C Coach - (2014-04-22) Interrupts
Reacting to external events as they happen. -
The Basic Postage doesn't support hardware interrupts which would allow the fastest possible reaction to an external outcome at no cost in extra time. Instead, a mecanism is provided which can check for some predetermined event after the execution of every PBASIC education. Information technology's the adjacent best affair.
Decoding a PWM point using the input capture module (PIC) past Matthew Watson.
- (2014-04-21) Propeller
Parallax P8X32A QuickStart Lath for Propeller MCU. -
Decoding a PWM bespeak using the input capture module (Film) by Matthew Watson.
What Is The Function Of The Ins Register In Bs2,
Source: http://www.numericana.com/answer/bs2.htm
Posted by: bookwolk1995.blogspot.com
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